High Bandwidth Memory (HBM): Why Micron and SK Hynix Are Essential for AI
Executive Summary and Market Importance
Artificial‑intelligence accelerators—GPUs, TPUs, and custom ASICs—require memory that can keep pace with petaflop‑scale compute. High Bandwidth Memory (HBM) delivers the combination of ultra‑wide I/O, low latency, and compact form factor that traditional DDR or GDDR cannot match. Global demand for HBM is projected to rise from roughly $1.2 billion in 2023 to over $4.5 billion by 2028, driven largely by data‑center AI servers and high‑performance computing (HPC) clusters. Micron Technology and SK Hynix together account for more than 70 % of the HBM market share, positioning them as critical enablers of the AI hardware ecosystem.
Technical Architecture and Engineering Breakthroughs
HBM’s core innovation is the 3‑D‑stacked die architecture. Multiple DRAM dies are bonded vertically using microscopic TSVs (through‑silicon vias) and connected to a silicon interposer that routes thousands of data lanes directly to the processor. This design reduces the distance that each bit travels, slashing access latency and allowing bandwidths that exceed 1 TB/s per stack in the latest HBM3E devices.
Key engineering milestones
- HBM1 (2015) – 1 Gb per die, 128‑bit wide I/O per stack, 150 GB/s bandwidth, fabricated on 28 nm.
- HBM2 (2016‑2018) – 2‑4 Gb per die, 256‑bit wide I/O, up to 256 GB/s per stack, moved to 20 nm and later 14 nm processes.
- HBM2E (2019‑2021) – 8 Gb per die, 512‑bit I/O, 460 GB/s per stack, introduced on 12 nm EUV.
- HBM3 (2022‑2023) – 16‑Gb per die, 1024‑bit I/O, 830 GB/s per stack, built on 8 nm and 7 nm nodes.
- HBM3E (2024‑present) – 24‑Gb per die, 1024‑bit I/O, 1.2 TB/s per stack, leveraging 6 nm and 5 nm processes.
Each generation adds more TSVs—rising from roughly 1,000 in HBM1 to over 4,000 in HBM3E—while shrinking the via diameter from 5 µm to under 2 µm. Power consumption per gigabyte has dropped from 0.9 W/GB in HBM1 to about 0.35 W/GB in HBM3E, a direct result of advanced low‑k dielectric materials and finer process nodes.
Why AI workloads need HBM
Training large language models (LLMs) involves moving terabytes of weight matrices between compute cores and memory every few microseconds. The bandwidth‑to‑capacity ratio of HBM (often >30 GB/s per GB) ensures that the compute units stay fed, while the stacked form factor fits within the limited real‑estate of a GPU or accelerator die. In contrast, GDDR6X, even at 21 Gbps per pin, cannot match the parallelism of HBM’s thousands of lanes, leading to bottlenecks that slow training epochs.
Financial Breakdown and Corporate Economics
Micron and SK Hynix have built distinct but complementary business models around HBM. Micron leverages its 28F‑DRAM platform and a vertically integrated fab to offer custom‑tailored stacks for Nvidia’s Hopper architecture and AMD’s CDNA3 GPUs. SK Hynix, with its massive 300 mm wafer line, supplies high‑volume HBM for data‑center GPUs and also provides foundry services for partner ASICs.
| Year | HBM Generation | Process Node (nm) | Bandwidth per Stack (GB/s) | Approx. Cost per GB ($) |
|---|---|---|---|---|
| 2015 | HBM1 | 28 | 150 | 45 |
| 2018 | HBM2 | 14‑20 | 256 | 32 |
| 2020 | HBM2E | 12 | 460 | 27 |
| 2023 | HBM3 | 7‑8 | 830 | 22 |
| 2025 | HBM3E | 5‑6 | 1,200 | 18 |
Revenue analysis shows Micron’s HBM sales grew from $120 million in 2020 to $620 million in 2023, a compound annual growth rate (CAGR) of 85 %. SK Hynix reported HBM revenue of $340 million in 2022, climbing to $1.1 billion by 2024, reflecting its larger capacity and earlier entry into HBM2E production. Both companies invest heavily in R&D: Micron allocated $1.3 billion to memory‑technology development in FY2023, while SK Hynix earmarked $2.2 billion for next‑generation 3‑D stacking.
Profit margins differ because of scale. SK Hynix’s economies of scale keep its gross margin on HBM around 38 %, whereas Micron’s more customized approach yields a margin near 30 %. The difference is offset by Micron’s higher average selling price (ASP) per gigabyte, which sits at $24 compared with SK Hynix’s $19 for comparable stacks.
Competitive Landscape and Supply Chain Interdependencies
The HBM market is not a free‑for‑all. Three forces shape it: technology leadership, fab capacity, and customer relationships.
Technology leadership
Micron’s 28F‑DRAM platform introduced a 1‑bit per cell architecture that reduces read/write latency by 15 % compared with legacy designs. SK Hynix’s “X‑band” TSV process, patented in 2019, enables tighter pitch and higher yield, which translates into lower cost per stack. Both firms have filed patents covering 5‑nm TSV etching, a step that will be required for HBM4, expected around 2027.
Fab capacity
SK Hynix operates three 300 mm fabs dedicated to 3‑D stacking, each capable of producing 1.2 million HBM stacks per month. Micron’s dedicated 28F line runs at 800,000 stacks per month but benefits from a flexible “fab‑as‑a‑service” model that can shift capacity to other memory products when demand dips.
Customer relationships
Nvidia’s partnership with Micron dates back to the Pascal generation, but the most recent agreement for the Hopper H100 GPU grants Micron exclusive rights to supply HBM3E for the “NVLink‑4” interconnect. AMD’s 2023 contract with SK Hynix covers the entire CDNA3 product line, guaranteeing a minimum of 250 million HBM stacks per year. These long‑term contracts reduce the risk of supply shortages that have plagued earlier AI hardware rollouts.
Emerging challengers
Samsung Electronics announced a prototype “HBM‑X” built on a 4 nm process, promising 1.5 TB/s per stack. However, the company has not yet entered volume production, and its design relies on a different interposer material that may require new testing standards. Intel’s “Foveros‑HBM” concept, which integrates compute and memory in a single package, remains in the research phase.
Supply chain resilience
Both Micron and SK Hynix have diversified their raw‑material sources for high‑purity silicon and copper. They maintain buffer inventories of TSV‑critical chemicals in Singapore and Taiwan, mitigating the impact of geopolitical disruptions. Recent trade‑policy shifts have prompted both firms to file “dual‑sourcing” plans with the U.S. Department of Commerce, ensuring that at least 60 % of HBM production can be shifted to domestic fabs within 12 months if required.
Frequently Asked Questions (FAQ)
What distinguishes HBM from GDDR memory?
HBM stacks memory vertically and connects to the processor through an interposer that offers thousands of parallel data lanes. GDDR places chips side‑by‑side on a PCB and uses fewer, higher‑speed lanes. The result is that HBM provides higher bandwidth per watt and a smaller footprint, which is essential for AI accelerators that pack many cores into a limited die area.
Why do AI vendors prefer Micron or SK Hynix HBM over other suppliers?
Both companies deliver proven yields at the advanced nodes required for the latest HBM generations. Their long‑standing relationships with Nvidia and AMD give them insight into the exact performance targets of new GPUs. Additionally, Micron’s ability to customize stack configurations and SK Hynix’s massive production capacity reduce lead times for large AI deployments.
How does the cost of HBM affect AI system pricing?
HBM’s per‑gigabyte price is higher than that of GDDR, but the performance advantage often translates into fewer accelerator cards needed for a given AI workload. A server that uses HBM‑equipped GPUs can achieve the same training throughput with 30‑40 % fewer GPUs, lowering overall system cost, power draw, and cooling requirements.
Will HBM remain relevant as AI models continue to grow?
Model sizes are expanding faster than memory capacity can keep up, prompting a shift toward hierarchical memory systems that combine HBM with on‑package SRAM and off‑chip DRAM. However, the latency and bandwidth characteristics of HBM make it the preferred “near‑processor” tier, and upcoming HBM4 and HBM5 specifications aim to double capacity while maintaining or improving bandwidth, ensuring its role in future AI hardware stacks.
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